DFT: JTAG, Boundary Scan & BIST
DFT: JTAG, Boundary Scan & BIST
💡 Key Takeaways
- Understand the purpose of Design for Test (DFT) and how it enhances fault detection and testability in digital designs.
- Describe the JTAG/boundary-scan architecture, including the Test Access Port (TAP), boundary-scan cells, and scan chain operation.
- Explain Built-In Self-Test (BIST) concepts, typical implementations (e.g., memory BIST), and how BIST accelerates testing.
- Identify the advantages and limitations of JTAG/boundary-scan and BIST compared with traditional in-circuit testing (ICT).
❓ Frequently Asked Questions
What does DFT stand for and why is it important in JTAG, Boundary Scan & BIST?
DFT stands for Design for Test. It embeds features that make devices easier to test (e.g., boundary-scan paths and built-in self-test), improving fault detection and manufacturability.
What is JTAG and what does it do?
JTAG is the IEEE 1149.1 Test Access Port and Boundary-Scan Architecture. It provides a serial interface to access a device's boundary-scan cells for testing, debugging, and programming.
What is boundary scan and how does it work?
Boundary scan surrounds each I/O pin with a scan cell. Test data are shifted in via TDI, clocked through by TCK, and read out via TDO to test interconnects on chips and boards.
What is Built-In Self-Test (BIST)?
BIST is self-test circuitry built into a device that can automatically generate and check test patterns to verify core logic or memory, reducing external test equipment.
How do JTAG, boundary scan, and BIST relate in a typical test flow?
JTAG provides the access for boundary-scan tests; boundary scan checks interconnections; BIST runs internal tests. Together they enable efficient testing of devices and boards.